1. Field of the Invention
The present invention relates to an internal power supply circuit and, more specifically, to an internal power supply circuit lowering an externally applied external power supply potential to a lower internal power supply potential and supplying the same to an internal circuitry of a semiconductor integrated circuit.
2. Description of the Background Art
Breakdown voltage of a transistor used in a semiconductor integrated circuit has been lowered as the device has been miniaturized. Accordingly, supply potential must be lowered. However, since the same power supply as that for ICs such as TTL (Transistor Transistor Logic) is used, the externally applied external power supply potential is maintained as it is, and an internal power supply potential is supplied to internal circuitry of the semiconductor integrated circuit by lowering the external power supply potential by using an internal power supply circuit provided on the chip.
FIG. 16 is a block diagram showing a structure of a DRAM (Dynamic Random Access Memory) including such a conventional internal power supply circuit.
Referring to FIG. 16, the DRAM includes an internal circuitry 1 including a memory cell array, sense amplifiers and address decoders, and an internal power supply circuit for supplying an internal power supply potential intVcc to the internal circuitry 1.
The internal power supply circuit includes a reference potential generating circuit 20, a control circuit 30, a main internal power supply potential generating circuit 40, an auxiliary internal power supply potential generating circuit 42, and an output node 50.
Reference potential generating circuit 20 is connected between an external power supply node 10 to which an external power supply potential extVcc (of, for example, 5 V) is applied and a ground node 11, and generates a constant reference potential Vref (of, for example, 3 V) based on the external power supply potential extVcc.
Main internal power supply potential generating circuit 40 is connected between external power supply node 10 and the ground node 11, and constantly generates at output node 50, an internal power supply potential intVcc (of, for example, 3 V) referring to the reference potential Vref from reference potential generating circuit 20.
Control circuit 30 generates a control signal .phi.1 in response to an external row address strobe signal ext/RAS. Internal circuitry 1 operates in response to an external row address strobe signal ext/RAS.
Auxiliary internal power supply potential generating circuit 42 is activated in response to control signal .phi.1 from control circuit 30, and when activated, generates an internal power supply potential intVcc at output node 50, referring to reference potential Vref.
Main internal power supply potential generating circuit 40 has small current supplying capability. However, it always operates with small power consumption, and supplies a small amount of current which is constantly consumed by internal circuitry 1. Meanwhile, auxiliary internal power supply potential generating circuit 42 consumes much power. However, its current supplying capability is larger than that of the main internal power supply potential generating circuit 40. Auxiliary internal power supply potential generating circuit 42 does not operate in the normal state (standby state) and operates only when internal circuitry 1 operates to consume a large amount of current.
Accordingly, current consumption at the standby state, when internal circuit 1 is not operating, is very small, and necessary current is supplied only when internal circuitry 1 operates. Thus, the internal power supply circuit as a whole does not match consume power.
The structure and operation of the internal power supply circuit has been briefly described. Details will be given in the following.
FIG. 17 is a schematic diagram showing a structure of main internal power supply potential generating circuit 40 shown in FIG. 16. This main internal power supply potential generating circuit 40 is a generally known one which is disclosed, for example, in page 117 of Nikkei Micro Device, February, 1990.
Referring to FIG. 17, main internal power supply potential generating circuit 40 includes a P channel MOS transistor 401 connected between external power supply node 10 and output node 50, and a current mirror type differential amplifier circuit 402.
Differential amplifier circuit 402 compares internal power supply potential intVcc generated at output node 50 with reference potential Vref, and applies a control signal .phi.2 to the gate of P channel MOS transistor 401, which signal attains approximately to the ground potential when internal power supply potential intVcc is lower than reference potential Vref and which attains approximately to the external power supply potential extVcc when internal power supply potential intVcc is higher than the reference potential Vref.
Differential amplifier circuit 402 includes two P channel MOS transistors 403 and 404 constituting a current mirror, an N channel MOS transistor 405 having a gate receiving the reference potential Vref, an N channel MOS transistor 406 having a gate receiving internal power supply potential intVcc, and an N channel MOS transistor 407 having a gate receiving external power supply potential extVcc.
P channel MOS transistor 403 is connected between external power supply node 10 and output node 408. P channel MOS transistor 404 is connected to the gate of transistor 403, and has its gate and drain connected to each other and its source connected to external power supply node 10.
N channel MOS transistor 405 is connected in series with transistor 403. N channel MOS transistor 406 is connected in series with transistor 403. N channel MOS transistor 407 has its drain connected to the sources of transistors 405 and 406, and its source connected to the ground node 11. Since transistor 407 is constantly supplied with the external power supply potential extVcc at its gate, a constant current always flows between its source and drain.
What the main internal power supply potential generating circuit 40 has to do is to supply current (of, for example, several ten mA) consumed in internal circuitry 1 in the standby state. Therefore, the size of the P channel MOS transistor 401 for driving is minimized. In other words, the ratio of its channel width with respect to the channel length is minimized.
Similarly, the size of N channel MOS transistor 407 which is constantly conductive is made small. Consequently, through current flowing from external power supply node 10 through transistors 403, 405 and 407 to the ground node 11 as well, as the through current flowing from external power supply node 10 through transistors 404,406 and 407 to the ground node are reduced, whereby power consumption of differential amplifying circuit 402 is reduced.
FIG. 18 is a schematic diagram showing the structure of auxiliary internal power supply potential generating circuit 42 shown in FIG. 16.
Referring to FIG. 18, auxiliary internal power supply potential generating circuit 42 includes a P channel MOS transistor 421 connected between external power supply node 10 and output node 50, a current mirror type differential amplifying circuit 422 comparing internal power supply potential intVcc with reference potential Vref for controlling transistor 421, and a P channel MOS transistor 423 connected between external power supply node 10 and the gate of transistor 421.
Similarly to the above described differential amplifying circuit 402, differential amplifying circuit 422 includes two P channel MOS transistors 424 and 425 constituting a current mirror, and three N channel MOS transistors 426 to 428.
Auxiliary internal supply potential generating circuit 42 differs from the above described main internal supply potential generating circuit 40 in the following points. First, the size of driving transistor 421 is made larger than that of driving transistor 401 so that it has larger current driving capability.
Second, control signal .phi.1 from control circuit 30 is applied to the gate electrode of transistor 428 in differential amplifying circuit 422, transistor 428 is rendered conductive in response to control signal .phi.1, and the size of transistor 428 is made larger than that of transistor 407.
Third, a transistor 423 is provided. Transistor 423 receives at its gate the control signal .phi.1 from control circuit 30. Therefore, transistor 423 is rendered conductive when transistor 428 is non-conductive, while it is rendered non-conductive when transistor 428 is conductive.
Since control signal .phi.1 attains to the H level only when internal circuitry 1 operates, differential amplifying circuit 422 is inactivated in the standby state in which internal circuitry 1 is not operative, and transistor 421 is rendered non-conductive since external supply potential extVcc is applied to its gate.
When internal circuitry 1 operates, control signal .phi.1 attains to the H level, differential amplifying circuit 422 is activated and transistor 423 is rendered non-conductive, so that auxiliary internal power supply potential generating circuit 42 as a whole is activated.
The operation of the internal power supply circuit will be discussed in greater detail.
First, the operation when control signal 61 output from control circuit 30 is at L level will be described.
Reference potential generating circuit 20 receives external power supply potential extVcc from external power supply node 10 and generates a reference potential Vref.
Differential amplifying circuit 402 in main internal power supply potential generating circuit 40 receives the reference potential Vref and internal power supply potential intVcc from output node 50, and when internal power supply potential intVcc is lower than reference potential Vref, provides a control signal .phi.2 which is approximately at the ground potential through output node 408.
Control signal .phi.2 is applied to the gate of driving transistor 401, so that transistor 401 is rendered conductive. Consequently, charges are supplied from external power supply node 10 to output node 50 through transistor 401, so that potential intVcc of output node 50 increases.
Meanwhile, when internal power supply potential intVcc is higher than reference potential Vref, differential amplifying circuit 402 in main internal power supply potential generating circuit 40 provides a control signal .phi.2 which is approximately at the external power supply potential extVcc through output node 408. Consequently, driving transistor 401 is rendered non-conductive.
In this manner, when current is consumed in internal circuitry 1 and internal power supply potential intVcc becomes lower than reference potential Vref, main internal power supply potential generating circuit 40 supplies charges from external power supply node 10 to output node 50, and when internal power supply potential intVcc becomes higher than reference potential Vref, stops supply of the charges.
In auxiliary internal power supply potential generating circuit 42, when control signal .phi.1 at the L level is applied to the gate of transistor 428 of differential amplifying circuit 422, the transistor 428 is rendered non-conductive. Therefore, differential amplifying circuit 422 does not operate.
At this time, in differential amplifying circuit 422, potentials at gates of transistors 424 and 425 are increased to a potential (for example, 4 V) lower than the external power supply potential (for example, 5 V) by an absolute value (for example, 1 V) of the threshold voltage (for example, -1 V) of transistors 424 and 425, and transistors 424 and 425 are rendered non-conductive.
Accordingly, the potential No at output node 429 attains to a potential (for example, 2 V) lower than the reference potential Vref (for example, 3 V) applied to the gate of transistor 426 by the threshold voltage (for example, 1 V) of the transistor 426, so that transistor 426 is rendered non-conductive. At this time, the differential amplifying circuit 422 is at a stable state.
In such a stable state, potential No at output node 429 is applied to the gate of driving transistor 421, and therefore it may be rendered conductive at any time. Therefore, there is a possibility that external power supply node 10 and output node 50 are conducted, causing internal power supply potential intVcc to be the external power supply potential extVcc.
In order to prevent such event, P channel MOS transistor 423 is provided, which receives at its gate the control signal .phi.1. When control signal .phi.1 at the L level supplied to the gate of transistor 423, transistor 423 is rendered conductive, so that external power supply potential extVcc is applied to the gate of driving transistor 421.
In this manner, in auxiliary internal power supply potential generating circuit 42, its driving transistor is adapted to be non-conductive in the standby state. The operation when control signal .phi.1 from control circuit 30 is at H level will be described.
Main internal power supply potential generating circuit 40 operates in the same manner as described above, regardless of the state of control signal .phi.1. Auxiliary internal power supply potential generating circuit 42 operates in the same manner as main internal power supply potential generating circuit 40, as N channel MOS transistor 428 is rendered conductive and P channel MOS transistor 423 is non-conductive.
The operation of the internal power supply circuit will be described with reference to the timing chart of FIG. 19.
Referring to FIG. 19(a), before time t0, when external row address strobe signal ext/RAS is at H level, in other words, in the standby state, control circuit 30 provides a control signal .phi.1 at the L level as shown in FIG. 19(b) in response to the row address strobe signal ext/RAS of the H level.
At this time, as described above, auxiliary internal power supply potential generating circuit 42 does not operate, and only the main internal power supply potential generating circuit 40 operates. Therefore, the potential No at output node 429 of auxiliary internal power supply potential generating circuit 42 is set to the external power supply potential extVcc by means of P channel MOS transistor 423, as shown in FIG. 19(c).
Thereafter, referring to FIG. 19(a), at time t0, when row address strobe signal ext/RAS falls to the L level, internal circuitry 1 starts its operation. Accordingly, current of about 100 mA in average and several hundred mA at most is consumed, as shown in FIG. 19(d), and internal power supply potential intVcc lowers a little as shown in FIG. 19(e).
In response to the row address strobe signal ext/RAS at the L level, control circuit 30 provides a control signal .phi.1 at the H level, as shown in FIG. 19(b). Consequently, transistor 428 in auxiliary internal power supply potential generating circuit 42 is rendered conductive, and transistor 423 is rendered non-conductive. Consequently, Potential No at output node 429 gradually lowers as shown in FIG. 19(c), and after the lapse of time At from time t0, it attains to a potential lower than external power supply potential extVcc by the absolute value .vertline.Vtp.vertline. of the threshold voltage of driving transistor 421.
Consequently, driving transistor 421 is rendered conductive, charges are supplied to the output node 50, and therefore internal power supply potential intVcc increases as shown in FIG. 19(e).
At time t1, when operation of internal circuitry 1 ends and current consumption is reduced, internal power supply potential intVcc increases. Accordingly, potential No at output node 429 of differential amplifying circuit 422 increases to a potential lower than the external power supply potential extVcc by the absolute value .vertline.Vtp.vertline. of the threshold voltage of P channel MOS transistor 421, as shown in FIG. 19(c). Consequently, driving transistor 421 is rendered non-conductive, and supply of charges to output node 50 is stopped.
Then, at time t2, when row address strobe signal ext/RAS attains to the H level, reset current flows in internal circuitry 1 from time t2 to t3, as shown in FIG. 19(d).
Taking into account the reset current, control signal .phi.1 output from control circuit 30 falls to the L level at time t4 after a prescribed time period from time t2 at which row address strobe signal ext/RAS rises to H level, as shown in FIG. 19(b).
In the above described conventional internal power supply circuit, when control signal .phi.1 from control circuit 30 rises from L level to H level at time t0 as shown in FIG. 19(b), the potential No at output node 429 of differential amplifying circuit 422, or the potential at the gate of driving transistor 421 begins to lower as shown in FIG. 19(c), and it further lowers to a potential extVcc--.vertline.Vtp.vertline. which is lower than the external power supply potential by the absolute value of the threshold voltage of driving transistor 421, and at this time, transistor 421 is rendered conductive for the first time so that charges are supplied from external power supply node 10 to output node 50.
Now, the channel width of transistor 421 is made large so as to increase current driving capability. Therefore, it has large gate capacitance and it takes time At as shown in FIG. 19(c) for the potential No of output node 429 to attain to sufficiently low potential as to render transistor 421 conductive.
On the other hand, internal circuitry 1 starts its operation, and therefore current consumption increases. Accordingly, internal power supply potential intVcc decreases from a prescribed potential (for example from 3 V to 2 V) during the time .DELTA.t until the auxiliary internal power supply potential generating circuit starts supply of charges to output node 50, which leads to possible malfunction of internal circuitry 1.
In Japanese Patent Laying-Open No. 3-194797, a semiconductor memory device is disclosed in which base potential of an NPN transistor is set high in advance in a reference potential generating circuit for determining whether or not a redundancy circuit is to be used, allowing quick rise of word lines when the redundancy circuit is used.
Japanese Patent Laying-Open No. 4-64989 discloses a semiconductor memory device including a current mirror circuit for amplifying a signal read on a data bus in which, to the gate of transistors constituting the current mirror, a voltage smaller than the threshold voltage thereof is applied, so that the current mirror circuit can be activated quickly.
By contrast, the present invention relates to an improvement of an internal power supply circuit in which internal power supply potential is provided by lowering an external power supply potential.